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authorGabe Black <gblack@eecs.umich.edu>2012-01-07 02:15:35 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-07 02:15:35 -0800
commitec936364b7238cddea7734ea79c6e04b52a683c6 (patch)
tree788fc19c3ba599d6f39d3990769888a0650be5ff /src/cpu/o3/cpu.cc
parent36a822f08e88483b41af214ace4fd3dccf3aa8cb (diff)
parent9b52717a92ed9592bd98a41683509f538262a5c7 (diff)
downloadgem5-ec936364b7238cddea7734ea79c6e04b52a683c6.tar.xz
Merge with the main repository again.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bb5ccc17e..5d3af6c70 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -438,6 +438,12 @@ FullO3CPU<Impl>::regStats()
"to idling")
.prereq(idleCycles);
+ quiesceCycles
+ .name(name() + ".quiesceCycles")
+ .desc("Total number of cycles that CPU has spent quiesced or waiting "
+ "for an interrupt")
+ .prereq(quiesceCycles);
+
// Number of Instructions simulated
// --------------------------------
// Should probably be in Base CPU but need templated
@@ -682,6 +688,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
activityRec.activity();
fetch.wakeFromQuiesce();
+ quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+
lastActivatedCycle = curTick();
_status = Running;
@@ -716,6 +724,9 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
unscheduleTickEvent();
+
+ DPRINTF(Quiesce, "Suspending Context\n");
+ lastRunningCycle = curTick();
_status = Idle;
}
@@ -1193,6 +1204,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
+
+ lastRunningCycle = curTick();
}
template <class Impl>