diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-21 20:35:25 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-21 20:35:25 +0000 |
commit | 49490b334af3bc145071a9a81f37012e7693af59 (patch) | |
tree | 7f07517e6d03bc004955f6a40a6c9dd3e02f7488 /src/cpu/o3/cpu.cc | |
parent | 470a6a9a74eb28a5052e6492c0a3aa9724c57500 (diff) | |
parent | afd00820004984de085a727e60e25742a69d9c51 (diff) | |
download | gem5-49490b334af3bc145071a9a81f37012e7693af59.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
src/cpu/o3/fetch_impl.hh:
hand merge
--HG--
extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r-- | src/cpu/o3/cpu.cc | 40 |
1 files changed, 30 insertions, 10 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 9e1b5d132..6a3eb9c43 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -694,7 +694,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid) // Squash Throughout Pipeline InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; - fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, true, tid); + fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); decode.squash(tid); rename.squash(squash_seq_num, tid); iew.squash(tid); @@ -1150,6 +1150,20 @@ FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) template <class Impl> uint64_t +FullO3CPU<Impl>::readMicroPC(unsigned tid) +{ + return commit.readMicroPC(tid); +} + +template <class Impl> +void +FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) +{ + commit.setMicroPC(new_PC, tid); +} + +template <class Impl> +uint64_t FullO3CPU<Impl>::readNextPC(unsigned tid) { return commit.readNextPC(tid); @@ -1177,6 +1191,20 @@ FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) } template <class Impl> +uint64_t +FullO3CPU<Impl>::readNextMicroPC(unsigned tid) +{ + return commit.readNextMicroPC(tid); +} + +template <class Impl> +void +FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) +{ + commit.setNextMicroPC(new_PC, tid); +} + +template <class Impl> typename FullO3CPU<Impl>::ListIt FullO3CPU<Impl>::addInst(DynInstPtr &inst) { @@ -1224,9 +1252,7 @@ FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) template <class Impl> void -FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, - bool squash_delay_slot, - const InstSeqNum &delay_slot_seq_num) +FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) { DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" " list.\n", tid); @@ -1257,12 +1283,6 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, while (inst_it != end_it) { assert(!instList.empty()); -#if ISA_HAS_DELAY_SLOT - if(!squash_delay_slot && - delay_slot_seq_num >= (*inst_it)->seqNum) { - break; - } -#endif squashInstIt(inst_it, tid); inst_it--; |