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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-02-15 17:40:08 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-02-15 17:40:08 -0500
commit1eec115c31395e2819c073a1859d75eb5933dac2 (patch)
tree503552557b8a5504bbb9aa9a3515b0bb398a97fc /src/cpu/o3/cpu.cc
parent1c7aa665bfc678c33cc05829acc52aebb1d2612c (diff)
downloadgem5-1eec115c31395e2819c073a1859d75eb5933dac2.tar.xz
cpu: Refactor memory system checks
CPUs need to test that the memory system is in the right mode in two places, when the CPU is initialized (unless it's switched out) and on a drainResume(). This led to some code duplication in the CPU models. This changeset introduces the verifyMemoryMode() method which is called by BaseCPU::init() if the CPU isn't switched out. The individual CPU models are responsible for calling this method when resuming from a drain as this code is CPU model specific.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 393b9a189..53250d495 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -646,12 +646,6 @@ FullO3CPU<Impl>::init()
{
BaseCPU::init();
- if (!params()->switched_out &&
- system->getMemoryMode() != Enums::timing) {
- fatal("The O3 CPU requires the memory system to be in "
- "'timing' mode.\n");
- }
-
for (ThreadID tid = 0; tid < numThreads; ++tid) {
// Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
@@ -1262,11 +1256,7 @@ FullO3CPU<Impl>::drainResume()
return;
DPRINTF(Drain, "Resuming...\n");
-
- if (system->getMemoryMode() != Enums::timing) {
- fatal("The O3 CPU requires the memory system to be in "
- "'timing' mode.\n");
- }
+ verifyMemoryMode();
fetch.drainResume();
commit.drainResume();
@@ -1323,6 +1313,16 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
template <class Impl>
+void
+FullO3CPU<Impl>::verifyMemoryMode() const
+{
+ if (system->getMemoryMode() != Enums::timing) {
+ fatal("The O3 CPU requires the memory system to be in "
+ "'timing' mode.\n");
+ }
+}
+
+template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{