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| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
| commit | 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (patch) | |
| tree | a736f3746d5c38bdc98d6fb8589113556271d486 /src/cpu/o3/cpu.cc | |
| parent | 69d419f31383ac7801e1debb62d5bbf7cb899e3c (diff) | |
| download | gem5-3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98.tar.xz | |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c5421302d..9de1bf6b4 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -241,6 +241,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) TheISA::NumMiscRegs * numThreads, TheISA::ZeroReg), + isa(numThreads, NULL), + icachePort(&fetch, this), dcachePort(&iew.ldstQueue, this), @@ -340,6 +342,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) for (ThreadID tid = 0; tid < numThreads; tid++) { bool bindRegs = (tid <= active_threads - 1); + isa[tid] = params->isa[tid]; + commitRenameMap[tid].init(TheISA::NumIntRegs, params->numPhysIntRegs, lreg_idx, //Index for Logical. Regs @@ -1285,7 +1289,7 @@ template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return this->isa[tid].readMiscRegNoEffect(misc_reg); + return this->isa[tid]->readMiscRegNoEffect(misc_reg); } template <class Impl> @@ -1293,7 +1297,7 @@ TheISA::MiscReg FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) { miscRegfileReads++; - return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); + return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); } template <class Impl> @@ -1301,7 +1305,7 @@ void FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->isa[tid].setMiscRegNoEffect(misc_reg, val); + this->isa[tid]->setMiscRegNoEffect(misc_reg, val); } template <class Impl> @@ -1310,7 +1314,7 @@ FullO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { miscRegfileWrites++; - this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); + this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); } template <class Impl> |