Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.

First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used.  These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
    Add in option USE_CHECKER to allow for not compiling in checker code.  The checker is enabled through this option instead of through the CPU_MODELS list.  However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
    Name change for DetailedCPU to DetailedO3CPU.  Also include option for max tick.
src/base/traceflags.py:
    Add in O3CPU trace flag.
src/cpu/SConscript:
    Rename AlphaFullCPU to AlphaO3CPU.

    Only include checker sources if they're necessary.  Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
    Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
    Also #ifdef the checker code so it doesn't need to be included if it's not selected.

--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a

1 files changed, 34 insertions, 31 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 788c6b164..430078860 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -29,6 +29,7 @@
  */
 
 #include "config/full_system.hh"
+#include "config/use_checker.hh"
 
 #if FULL_SYSTEM
 #include "sim/system.hh"
@@ -50,13 +51,13 @@
 using namespace std;
 using namespace TheISA;
 
-BaseFullCPU::BaseFullCPU(Params *params)
+BaseO3CPU::BaseO3CPU(Params *params)
     : BaseCPU(params), cpu_id(0)
 {
 }
 
 void
-BaseFullCPU::regStats()
+BaseO3CPU::regStats()
 {
     BaseCPU::regStats();
 }
@@ -83,7 +84,7 @@ FullO3CPU<Impl>::TickEvent::description()
 
 template <class Impl>
 FullO3CPU<Impl>::FullO3CPU(Params *params)
-    : BaseFullCPU(params),
+    : BaseO3CPU(params),
       tickEvent(this),
       removeInstsThisCycle(false),
       fetch(params),
@@ -131,6 +132,9 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 {
     _status = Idle;
 
+    checker = NULL;
+
+#if USE_CHECKER
     if (params->checker) {
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
@@ -138,9 +142,8 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 #if FULL_SYSTEM
         checker->setSystem(params->system);
 #endif
-    } else {
-        checker = NULL;
     }
+#endif
 
 #if !FULL_SYSTEM
     thread.resize(number_of_threads);
@@ -261,9 +264,9 @@ template <class Impl>
 void
 FullO3CPU<Impl>::fullCPURegStats()
 {
-    BaseFullCPU::regStats();
+    BaseO3CPU::regStats();
 
-    // Register any of the FullCPU's stats here.
+    // Register any of the O3CPU's stats here.
     timesIdled
         .name(name() + ".timesIdled")
         .desc("Number of times that the entire CPU went into an idle state and"
@@ -319,7 +322,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::tick()
 {
-    DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
+    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
 
     ++numCycles;
 
@@ -418,7 +421,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::insertThread(unsigned tid)
 {
-    DPRINTF(FullCPU,"[tid:%i] Initializing thread data");
+    DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
     // Will change now that the PC and thread state is internal to the CPU
     // and not in the ThreadContext.
 #if 0
@@ -465,7 +468,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::removeThread(unsigned tid)
 {
-    DPRINTF(FullCPU,"[tid:%i] Removing thread data");
+    DPRINTF(O3CPU,"[tid:%i] Removing thread data");
 #if 0
     //Unbind Int Regs from Rename Map
     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
@@ -511,37 +514,37 @@ template <class Impl>
 void
 FullO3CPU<Impl>::activateWhenReady(int tid)
 {
-    DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming"
+    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
             "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
             tid);
 
     bool ready = true;
 
     if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
-        DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
                 "Phys. Int. Regs.\n",
                 tid);
         ready = false;
     } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
-        DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
                 "Phys. Float. Regs.\n",
                 tid);
         ready = false;
     } else if (commit.rob->numFreeEntries() >=
                commit.rob->entryAmount(activeThreads.size() + 1)) {
-        DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
                 "ROB entries.\n",
                 tid);
         ready = false;
     } else if (iew.instQueue.numFreeEntries() >=
                iew.instQueue.entryAmount(activeThreads.size() + 1)) {
-        DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
                 "IQ entries.\n",
                 tid);
         ready = false;
     } else if (iew.ldstQueue.numFreeEntries() >=
                iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
-        DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
                 "LSQ entries.\n",
                 tid);
         ready = false;
@@ -575,7 +578,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
     if (isActive == activeThreads.end()) {
         //May Need to Re-code this if the delay variable is the
         //delay needed for thread to activate
-        DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
+        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
                 tid);
 
         activeThreads.push_back(tid);
@@ -597,7 +600,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::suspendContext(int tid)
 {
-    DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid);
+    DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
     unscheduleTickEvent();
     _status = Idle;
 /*
@@ -606,7 +609,7 @@ FullO3CPU<Impl>::suspendContext(int tid)
         activeThreads.begin(), activeThreads.end(), tid);
 
     if (isActive != activeThreads.end()) {
-        DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
+        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
                 tid);
         activeThreads.erase(isActive);
     }
@@ -617,14 +620,14 @@ template <class Impl>
 void
 FullO3CPU<Impl>::deallocateContext(int tid)
 {
-    DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid);
+    DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
 /*
     //Remove From Active List, if Active
     list<unsigned>::iterator isActive = find(
         activeThreads.begin(), activeThreads.end(), tid);
 
     if (isActive != activeThreads.end()) {
-        DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
+        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
                 tid);
         activeThreads.erase(isActive);
 
@@ -637,14 +640,14 @@ template <class Impl>
 void
 FullO3CPU<Impl>::haltContext(int tid)
 {
-    DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid);
+    DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
 /*
     //Remove From Active List, if Active
     list<unsigned>::iterator isActive = find(
         activeThreads.begin(), activeThreads.end(), tid);
 
     if (isActive != activeThreads.end()) {
-        DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
+        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
                 tid);
         activeThreads.erase(isActive);
 
@@ -730,7 +733,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
     if (isActive == activeThreads.end()) {
         //May Need to Re-code this if the delay variable is the delay
         //needed for thread to activate
-        DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
+        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
                 tid);
 
         activeThreads.push_back(tid);
@@ -958,7 +961,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
 {
-    DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
+    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
             "[sn:%lli]\n",
             inst->threadNumber, inst->readPC(), inst->seqNum);
 
@@ -972,7 +975,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
 {
-    DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction"
+    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
             " list.\n", tid);
 
     ListIt end_it;
@@ -982,12 +985,12 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
     if (instList.empty()) {
         return;
     } else if (rob.isEmpty(/*tid*/)) {
-        DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n");
+        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
         end_it = instList.begin();
         rob_empty = true;
     } else {
         end_it = (rob.readTailInst(tid))->getInstListIt();
-        DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n");
+        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
     }
 
     removeInstsThisCycle = true;
@@ -1026,7 +1029,7 @@ FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
 
     inst_iter--;
 
-    DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
+    DPRINTF(O3CPU, "Deleting instructions from instruction "
             "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
             tid, seq_num, (*inst_iter)->seqNum);
 
@@ -1048,7 +1051,7 @@ inline void
 FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
 {
     if ((*instIt)->threadNumber == tid) {
-        DPRINTF(FullCPU, "FullCPU: Squashing instruction, "
+        DPRINTF(O3CPU, "Squashing instruction, "
                 "[tid:%i] [sn:%lli] PC %#x\n",
                 (*instIt)->threadNumber,
                 (*instIt)->seqNum,
@@ -1069,7 +1072,7 @@ void
 FullO3CPU<Impl>::cleanUpRemovedInsts()
 {
     while (!removeList.empty()) {
-        DPRINTF(FullCPU, "FullCPU: Removing instruction, "
+        DPRINTF(O3CPU, "Removing instruction, "
                 "[tid:%i] [sn:%lli] PC %#x\n",
                 (*removeList.front())->threadNumber,
                 (*removeList.front())->seqNum,