Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)

Still need to add some code to fetch & commit stages

src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Add nextNPC

--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7

1 files changed, 17 insertions, 0 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 788c6b164..d5538cdf0 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #include "config/full_system.hh"
@@ -922,6 +923,22 @@ FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
     commit.setNextPC(val, tid);
 }
 
+#if THE_ISA != ALPHA_ISA
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readNextNPC(unsigned tid)
+{
+    return commit.readNextNPC(tid);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
+{
+    commit.setNextNPC(val, tid);
+}
+#endif
+
 template <class Impl>
 typename FullO3CPU<Impl>::ListIt
 FullO3CPU<Impl>::addInst(DynInstPtr &inst)