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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-06 16:52:05 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-06 16:52:05 -0400 |
commit | 1ccfdb442ff34f9f2b38ee7716b7baee99a397c2 (patch) | |
tree | 1cfdd49a4a8c2e5e89dd66adb98acec93c745e8f /src/cpu/o3/cpu.cc | |
parent | a1d208a65de95ee14c52fdc6ca9401642e07293d (diff) | |
download | gem5-1ccfdb442ff34f9f2b38ee7716b7baee99a397c2.tar.xz |
Timing cache works for hello world test.
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))
src/cpu/simple/timing.cc:
Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
Handle marking MSHR's in service
Add support for getting CSHR's
src/mem/cache/base_cache.hh:
Make these functions visible at the base cache level
src/mem/cache/cache.hh:
make the functions virtual
src/mem/cache/cache_impl.hh:
Rename the function to make sense
src/mem/packet.hh:
Accidentally clearing the needsResponse field when sending a response back.
--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
Diffstat (limited to 'src/cpu/o3/cpu.cc')
0 files changed, 0 insertions, 0 deletions