cpu: Physical register structural + flat indexing

Mimic the changes done on the architectural register indexes on the
physical register indexes. This is specific to the O3 model. The
structure, called PhysRegId, contains a register class, a register
index and a flat register index. The flat register index is kept
because it is useful in some cases where the type of register is not
important (dependency graph and scoreboard for example). Instead
of directly using the structure, most of the code is working with
a const PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId
objects are stored in the regFile.

Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2701
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 34 insertions, 35 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index a2d8147ea..6e9accdd5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -180,8 +180,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
       rob(this, params),
 
       scoreboard(name() + ".scoreboard",
-                 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
-                 TheISA::ZeroReg, TheISA::ZeroReg),
+                 regFile.totalNumPhysRegs()),
 
       isa(numThreads, NULL),
 
@@ -300,19 +299,19 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
         for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
             // Note that we can't use the rename() method because we don't
             // want special treatment for the zero register at this point
-            PhysRegIndex phys_reg = freeList.getIntReg();
+            PhysRegIdPtr phys_reg = freeList.getIntReg();
             renameMap[tid].setIntEntry(ridx, phys_reg);
             commitRenameMap[tid].setIntEntry(ridx, phys_reg);
         }
 
         for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
-            PhysRegIndex phys_reg = freeList.getFloatReg();
+            PhysRegIdPtr phys_reg = freeList.getFloatReg();
             renameMap[tid].setFloatEntry(ridx, phys_reg);
             commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
         }
 
         for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
-            PhysRegIndex phys_reg = freeList.getCCReg();
+            PhysRegIdPtr phys_reg = freeList.getCCReg();
             renameMap[tid].setCCEntry(ridx, phys_reg);
             commitRenameMap[tid].setCCEntry(ridx, phys_reg);
         }
@@ -791,7 +790,7 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
 
     for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
          reg_id.regIdx++) {
-        PhysRegIndex phys_reg = freeList.getIntReg();
+        PhysRegIdPtr phys_reg = freeList.getIntReg();
         renameMap[tid].setEntry(reg_id, phys_reg);
         scoreboard.setReg(phys_reg);
     }
@@ -799,7 +798,7 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     //Bind Float Regs to Rename Map
     for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
          reg_id.regIdx++) {
-        PhysRegIndex phys_reg = freeList.getFloatReg();
+        PhysRegIdPtr phys_reg = freeList.getFloatReg();
         renameMap[tid].setEntry(reg_id, phys_reg);
         scoreboard.setReg(phys_reg);
     }
@@ -807,7 +806,7 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     //Bind condition-code Regs to Rename Map
     for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
          reg_id.regIdx++) {
-        PhysRegIndex phys_reg = freeList.getCCReg();
+        PhysRegIdPtr phys_reg = freeList.getCCReg();
         renameMap[tid].setEntry(reg_id, phys_reg);
         scoreboard.setReg(phys_reg);
     }
@@ -845,7 +844,7 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     // Unbind Int Regs from Rename Map
     for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
          reg_id.regIdx++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
+        PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
@@ -853,7 +852,7 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     // Unbind Float Regs from Rename Map
     for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
          reg_id.regIdx++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
+        PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
@@ -861,7 +860,7 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     // Unbind condition-code Regs from Rename Map
     for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
          reg_id.regIdx++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
+        PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
@@ -1234,66 +1233,66 @@ FullO3CPU<Impl>::setMiscReg(int misc_reg,
 
 template <class Impl>
 uint64_t
-FullO3CPU<Impl>::readIntReg(int reg_idx)
+FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
 {
     intRegfileReads++;
-    return regFile.readIntReg(reg_idx);
+    return regFile.readIntReg(phys_reg);
 }
 
 template <class Impl>
 FloatReg
-FullO3CPU<Impl>::readFloatReg(int reg_idx)
+FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
 {
     fpRegfileReads++;
-    return regFile.readFloatReg(reg_idx);
+    return regFile.readFloatReg(phys_reg);
 }
 
 template <class Impl>
 FloatRegBits
-FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
+FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
 {
     fpRegfileReads++;
-    return regFile.readFloatRegBits(reg_idx);
+    return regFile.readFloatRegBits(phys_reg);
 }
 
 template <class Impl>
 CCReg
-FullO3CPU<Impl>::readCCReg(int reg_idx)
+FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
 {
     ccRegfileReads++;
-    return regFile.readCCReg(reg_idx);
+    return regFile.readCCReg(phys_reg);
 }
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
+FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
 {
     intRegfileWrites++;
-    regFile.setIntReg(reg_idx, val);
+    regFile.setIntReg(phys_reg, val);
 }
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
+FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
 {
     fpRegfileWrites++;
-    regFile.setFloatReg(reg_idx, val);
+    regFile.setFloatReg(phys_reg, val);
 }
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
+FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
 {
     fpRegfileWrites++;
-    regFile.setFloatRegBits(reg_idx, val);
+    regFile.setFloatRegBits(phys_reg, val);
 }
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
+FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
 {
     ccRegfileWrites++;
-    regFile.setCCReg(reg_idx, val);
+    regFile.setCCReg(phys_reg, val);
 }
 
 template <class Impl>
@@ -1301,7 +1300,7 @@ uint64_t
 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
 {
     intRegfileReads++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
 
     return regFile.readIntReg(phys_reg);
 }
@@ -1311,7 +1310,7 @@ float
 FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
 {
     fpRegfileReads++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
 
     return regFile.readFloatReg(phys_reg);
 }
@@ -1321,7 +1320,7 @@ uint64_t
 FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
 {
     fpRegfileReads++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
 
     return regFile.readFloatRegBits(phys_reg);
 }
@@ -1331,7 +1330,7 @@ CCReg
 FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
 {
     ccRegfileReads++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
 
     return regFile.readCCReg(phys_reg);
 }
@@ -1341,7 +1340,7 @@ void
 FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
 {
     intRegfileWrites++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
 
     regFile.setIntReg(phys_reg, val);
 }
@@ -1351,7 +1350,7 @@ void
 FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
 {
     fpRegfileWrites++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
 
     regFile.setFloatReg(phys_reg, val);
 }
@@ -1361,7 +1360,7 @@ void
 FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
 {
     fpRegfileWrites++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
 
     regFile.setFloatRegBits(phys_reg, val);
 }
@@ -1371,7 +1370,7 @@ void
 FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
 {
     ccRegfileWrites++;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
+    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
 
     regFile.setCCReg(phys_reg, val);
 }