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authorNathanael Premillieu <nathanael.premillieu@arm.com>2017-04-05 12:46:06 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch)
tree7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/o3/cpu.cc
parent864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff)
downloadgem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc39
1 files changed, 19 insertions, 20 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8d38ed1f2..a2d8147ea 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -788,29 +788,27 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
src_tc = tcBase(tid);
//Bind Int Regs to Rename Map
- for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
- PhysRegIndex phys_reg = freeList.getIntReg();
- renameMap[tid].setEntry(ireg,phys_reg);
+ for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
+ reg_id.regIdx++) {
+ PhysRegIndex phys_reg = freeList.getIntReg();
+ renameMap[tid].setEntry(reg_id, phys_reg);
scoreboard.setReg(phys_reg);
}
//Bind Float Regs to Rename Map
- int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
- for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
+ for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
+ reg_id.regIdx++) {
PhysRegIndex phys_reg = freeList.getFloatReg();
-
- renameMap[tid].setEntry(freg,phys_reg);
+ renameMap[tid].setEntry(reg_id, phys_reg);
scoreboard.setReg(phys_reg);
}
//Bind condition-code Regs to Rename Map
- max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
- for (int creg = TheISA::CC_Reg_Base;
- creg < max_reg; creg++) {
+ for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
+ reg_id.regIdx++) {
PhysRegIndex phys_reg = freeList.getCCReg();
-
- renameMap[tid].setEntry(creg,phys_reg);
+ renameMap[tid].setEntry(reg_id, phys_reg);
scoreboard.setReg(phys_reg);
}
@@ -845,24 +843,25 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
// in SMT workloads.
// Unbind Int Regs from Rename Map
- for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
- PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
+ for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
+ reg_id.regIdx++) {
+ PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
scoreboard.unsetReg(phys_reg);
freeList.addReg(phys_reg);
}
// Unbind Float Regs from Rename Map
- int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
- for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
- PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
+ for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
+ reg_id.regIdx++) {
+ PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
scoreboard.unsetReg(phys_reg);
freeList.addReg(phys_reg);
}
// Unbind condition-code Regs from Rename Map
- max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
- for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
- PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
+ for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
+ reg_id.regIdx++) {
+ PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
scoreboard.unsetReg(phys_reg);
freeList.addReg(phys_reg);
}