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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
| tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/cpu/o3/cpu.cc | |
| parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
| download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz | |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 621b6c1b9..2f8869b6f 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1180,14 +1180,14 @@ template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return this->regFile.readMiscRegNoEffect(misc_reg, tid); + return this->isa[tid].readMiscRegNoEffect(misc_reg); } template <class Impl> TheISA::MiscReg FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); } template <class Impl> @@ -1195,7 +1195,7 @@ void FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); + this->isa[tid].setMiscRegNoEffect(misc_reg, val); } template <class Impl> @@ -1203,7 +1203,7 @@ void FullO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); } template <class Impl> |