add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models

src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a

1 files changed, 7 insertions, 3 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index af032132e..19ab7f4c5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -181,7 +181,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
                   params->activity),
 
       globalSeqNum(1),
-
 #if FULL_SYSTEM
       system(params->system),
       physmem(system->physmem),
@@ -322,6 +321,11 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 
     lastActivatedCycle = -1;
 
+    // Give renameMap & rename stage access to the freeList;
+    //for (int i=0; i < numThreads; i++) {
+        //globalSeqNum[i] = 1;
+        //}
+
     contextSwitch = false;
 }
 
@@ -627,7 +631,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
     //Set PC/NPC/NNPC
     setPC(src_tc->readPC(), tid);
     setNextPC(src_tc->readNextPC(), tid);
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
     setNextNPC(src_tc->readNextNPC(), tid);
 #endif
 
@@ -1197,7 +1201,7 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
     while (inst_it != end_it) {
         assert(!instList.empty());
 
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
         if(!squash_delay_slot &&
            delay_slot_seq_num >= (*inst_it)->seqNum) {
             break;