summaryrefslogtreecommitdiff
path: root/src/cpu/o3/cpu.cc
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2015-02-16 03:33:28 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-02-16 03:33:28 -0500
commitd0e1b8a19c6d58a49e5288938e9b12f3f10b9f51 (patch)
treef990864e7fb9ffaf11e3895e8337737941390aa2 /src/cpu/o3/cpu.cc
parent07ce60bdfa57eedf00f533704b5a2da3fa01b553 (diff)
downloadgem5-d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51.tar.xz
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b48c66c37..434bfd7da 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1205,7 +1205,7 @@ FullO3CPU<Impl>::verifyMemoryMode() const
template <class Impl>
TheISA::MiscReg
-FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
return this->isa[tid]->readMiscRegNoEffect(misc_reg);
}