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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/cpu.cc | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r-- | src/cpu/o3/cpu.cc | 88 |
1 files changed, 85 insertions, 3 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 3e33e139a..f379b1068 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -225,7 +225,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) commit(this, params), regFile(params->numPhysIntRegs, - params->numPhysFloatRegs), + params->numPhysFloatRegs, + params->numPhysCCRegs), freeList(name() + ".freelist", ®File), @@ -327,6 +328,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) //Make Sure That this a Valid Architeture assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); + assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); rename.setScoreboard(&scoreboard); iew.setScoreboard(&scoreboard); @@ -368,6 +370,12 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) renameMap[tid].setFloatEntry(ridx, phys_reg); commitRenameMap[tid].setFloatEntry(ridx, phys_reg); } + + for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { + PhysRegIndex phys_reg = freeList.getCCReg(); + renameMap[tid].setCCEntry(ridx, phys_reg); + commitRenameMap[tid].setCCEntry(ridx, phys_reg); + } } rename.setRenameMap(renameMap); @@ -555,6 +563,16 @@ FullO3CPU<Impl>::regStats() .desc("number of floating regfile writes") .prereq(fpRegfileWrites); + ccRegfileReads + .name(name() + ".cc_regfile_reads") + .desc("number of cc regfile reads") + .prereq(ccRegfileReads); + + ccRegfileWrites + .name(name() + ".cc_regfile_writes") + .desc("number of cc regfile writes") + .prereq(ccRegfileWrites); + miscRegfileReads .name(name() + ".misc_regfile_reads") .desc("number of misc regfile reads") @@ -842,13 +860,24 @@ FullO3CPU<Impl>::insertThread(ThreadID tid) } //Bind Float Regs to Rename Map - for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { + int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; + for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { PhysRegIndex phys_reg = freeList.getFloatReg(); renameMap[tid].setEntry(freg,phys_reg); scoreboard.setReg(phys_reg); } + //Bind condition-code Regs to Rename Map + max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; + for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; + creg < max_reg; creg++) { + PhysRegIndex phys_reg = freeList.getCCReg(); + + renameMap[tid].setEntry(creg,phys_reg); + scoreboard.setReg(phys_reg); + } + //Copy Thread Data Into RegFile //this->copyFromTC(tid); @@ -888,13 +917,24 @@ FullO3CPU<Impl>::removeThread(ThreadID tid) } // Unbind Float Regs from Rename Map - for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { + int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; + for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { PhysRegIndex phys_reg = renameMap[tid].lookup(freg); scoreboard.unsetReg(phys_reg); freeList.addReg(phys_reg); } + // Unbind condition-code Regs from Rename Map + max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; + for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; + creg < max_reg; creg++) { + PhysRegIndex phys_reg = renameMap[tid].lookup(creg); + + scoreboard.unsetReg(phys_reg); + freeList.addReg(phys_reg); + } + // Squash Throughout Pipeline DynInstPtr inst = commit.rob->readHeadInst(tid); InstSeqNum squash_seq_num = inst->seqNum; @@ -934,6 +974,7 @@ FullO3CPU<Impl>::activateWhenReady(ThreadID tid) bool ready = true; + // Should these all be '<' not '>='? This seems backwards... if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " "Phys. Int. Regs.\n", @@ -944,6 +985,11 @@ FullO3CPU<Impl>::activateWhenReady(ThreadID tid) "Phys. Float. Regs.\n", tid); ready = false; + } else if (freeList.numFreeCCRegs() >= TheISA::NumCCRegs) { + DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " + "Phys. CC. Regs.\n", + tid); + ready = false; } else if (commit.rob->numFreeEntries() >= commit.rob->entryAmount(activeThreads.size() + 1)) { DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " @@ -1366,6 +1412,14 @@ FullO3CPU<Impl>::readFloatRegBits(int reg_idx) } template <class Impl> +CCReg +FullO3CPU<Impl>::readCCReg(int reg_idx) +{ + ccRegfileReads++; + return regFile.readCCReg(reg_idx); +} + +template <class Impl> void FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) { @@ -1390,6 +1444,14 @@ FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) } template <class Impl> +void +FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) +{ + ccRegfileWrites++; + regFile.setCCReg(reg_idx, val); +} + +template <class Impl> uint64_t FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) { @@ -1420,6 +1482,16 @@ FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) } template <class Impl> +CCReg +FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) +{ + ccRegfileReads++; + PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); + + return regFile.readCCReg(phys_reg); +} + +template <class Impl> void FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) { @@ -1450,6 +1522,16 @@ FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) } template <class Impl> +void +FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) +{ + ccRegfileWrites++; + PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); + + regFile.setCCReg(phys_reg, val); +} + +template <class Impl> TheISA::PCState FullO3CPU<Impl>::pcState(ThreadID tid) { |