summaryrefslogtreecommitdiff
path: root/src/cpu/o3/cpu.cc
diff options
context:
space:
mode:
authorKorey Sewell <ksewell@umich.edu>2008-02-27 16:48:33 -0500
committerKorey Sewell <ksewell@umich.edu>2008-02-27 16:48:33 -0500
commit34715cc691e217016ccce9bd1383dac9cca7126f (patch)
tree5101e6352f059cca3bac738fcb73eac70c62f48a /src/cpu/o3/cpu.cc
parentfcfc8b8c4ff98d69aa15fba60e723a9a1c4cda42 (diff)
downloadgem5-34715cc691e217016ccce9bd1383dac9cca7126f.tar.xz
Fix offset in removeThread() function so that float registers start freeing up
from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. --HG-- extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
Diffstat (limited to 'src/cpu/o3/cpu.cc')
-rw-r--r--src/cpu/o3/cpu.cc5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8eb17d23b..ff1ee7920 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -682,7 +682,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
}
// Unbind Float Regs from Rename Map
- for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
+ for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
scoreboard.unsetReg(phys_reg);
@@ -695,8 +695,11 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
decode.squash(tid);
rename.squash(squash_seq_num, tid);
iew.squash(tid);
+ //iew.ldstQueue.squash(squash_seq_num, tid);
commit.rob->squash(squash_seq_num, tid);
+
+ assert(iew.instQueue.getCount(tid) == 0);
assert(iew.ldstQueue.getCount(tid) == 0);
// Reset ROB/IQ/LSQ Entries