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| author | Gabe Black <gabeblack@google.com> | 2018-11-19 17:20:31 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-12-20 19:27:51 +0000 |
| commit | 88bbabe93f339f9db301caf43bf2cca2a0e8048c (patch) | |
| tree | 66323afaa9348f392deafe11d88973fd3034001b /src/cpu/o3/cpu.cc | |
| parent | 67d58e81825d7dff17def2cfeedf5d958141be55 (diff) | |
| download | gem5-88bbabe93f339f9db301caf43bf2cca2a0e8048c.tar.xz | |
arch, cpu: Remove float type accessors.
Use the binary accessors instead.
Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/o3/cpu.cc')
| -rw-r--r-- | src/cpu/o3/cpu.cc | 42 |
1 files changed, 2 insertions, 40 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2f793453d..e5b8103ab 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1284,14 +1284,6 @@ FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) } template <class Impl> -FloatReg -FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) -{ - fpRegfileReads++; - return regFile.readFloatReg(phys_reg); -} - -template <class Impl> FloatRegBits FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) { @@ -1343,14 +1335,6 @@ FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) template <class Impl> void -FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) -{ - fpRegfileWrites++; - regFile.setFloatReg(phys_reg, val); -} - -template <class Impl> -void FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) { fpRegfileWrites++; @@ -1393,19 +1377,8 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) } template <class Impl> -float -FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) -{ - fpRegfileReads++; - PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( - RegId(FloatRegClass, reg_idx)); - - return regFile.readFloatReg(phys_reg); -} - -template <class Impl> uint64_t -FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) +FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid) { fpRegfileReads++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( @@ -1468,18 +1441,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) -{ - fpRegfileWrites++; - PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( - RegId(FloatRegClass, reg_idx)); - - regFile.setFloatReg(phys_reg, val); -} - -template <class Impl> -void -FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid) { fpRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( |