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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:39 -0400 |
| commit | b265d9925c123f0df50db98cf56dab6a3596b54b (patch) | |
| tree | 2b115ce862733a499c453352db3a6ae5b9f93cd6 /src/cpu/o3/cpu.hh | |
| parent | 1c2ee987f37f4aac16cd0ff3e3ceeff949066a94 (diff) | |
| download | gem5-b265d9925c123f0df50db98cf56dab6a3596b54b.tar.xz | |
Port: Align port names in C++ and Python
This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.
Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.
Diffstat (limited to 'src/cpu/o3/cpu.hh')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 41128110b..b1fd12a2e 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -141,7 +141,7 @@ class FullO3CPU : public BaseO3CPU public: /** Default constructor. */ IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) - : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch) + : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) { } protected: @@ -168,7 +168,7 @@ class FullO3CPU : public BaseO3CPU public: /** Default constructor. */ DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) - : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq) + : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) { } protected: |