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| author | Marc Orr <morr@cs.wisc.edu> | 2014-11-06 05:42:22 -0600 |
|---|---|---|
| committer | Marc Orr <morr@cs.wisc.edu> | 2014-11-06 05:42:22 -0600 |
| commit | bf80734b2ce080cd75f4b57be47e37465e8901f1 (patch) | |
| tree | 0ba9cbba64cd017e95b5a3f637d58435208ebc3c /src/cpu/o3/cpu.hh | |
| parent | 3947f88d0fa35d2134fa3e999e05bb184a01e396 (diff) | |
| download | gem5-bf80734b2ce080cd75f4b57be47e37465e8901f1.tar.xz | |
x86 isa: This patch attempts an implementation at mwait.
Mwait works as follows:
1. A cpu monitors an address of interest (monitor instruction)
2. A cpu calls mwait - this loads the cache line into that cpu's cache.
3. The cpu goes to sleep.
4. When another processor requests write permission for the line, it is
evicted from the sleeping cpu's cache. This eviction is forwarded to the
sleeping cpu, which then wakes up.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/cpu/o3/cpu.hh')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 96cd071e4..09b7db867 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -162,11 +162,13 @@ class FullO3CPU : public BaseO3CPU /** Pointer to LSQ. */ LSQ<Impl> *lsq; + FullO3CPU<Impl> *cpu; public: /** Default constructor. */ DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) - : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) + : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), + cpu(_cpu) { } protected: |