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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
| tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/cpu/o3/cpu.hh | |
| parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
| download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz | |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/cpu/o3/cpu.hh')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 5cf27df75..1289785dc 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -395,11 +395,11 @@ class FullO3CPU : public BaseO3CPU /** Get instruction asid. */ int getInstAsid(ThreadID tid) - { return regFile.miscRegs[tid].getInstAsid(); } + { return isa[tid].instAsid(); } /** Get data asid. */ int getDataAsid(ThreadID tid) - { return regFile.miscRegs[tid].getDataAsid(); } + { return isa[tid].dataAsid(); } #else /** Get instruction asid. */ int getInstAsid(ThreadID tid) @@ -603,6 +603,8 @@ class FullO3CPU : public BaseO3CPU /** Integer Register Scoreboard */ Scoreboard scoreboard; + TheISA::ISA isa[Impl::MaxThreads]; + public: /** Enum to give each stage a specific index, so when calling * activateStage() or deactivateStage(), they can specify which stage |