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| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-03 10:29:37 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:17 +0800 |
| commit | c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9 (patch) | |
| tree | 3a1cb356c61cc6366d20c46353ed494d8e49ba92 /src/cpu/o3/cpu.hh | |
| parent | cb5562bb15f32e9040eccb57271d86fddc614230 (diff) | |
| download | gem5-c0d7cca1d9895f1c3476ce9864584eb4fb2e6ee9.tar.xz | |
check loads using tainted registers, set USL dst as tainted
Diffstat (limited to 'src/cpu/o3/cpu.hh')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 23e6f7434..131655ecd 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -401,6 +401,7 @@ class FullO3CPU : public BaseO3CPU /** taint a register */ void setTaint(PhysRegIdPtr phys_reg); + bool regTainted(PhysRegIdPtr phys_reg); uint64_t readIntReg(PhysRegIdPtr phys_reg); |