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author | Iru Cai <mytbk920423@gmail.com> | 2019-04-02 16:28:08 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:17 +0800 |
commit | cb5562bb15f32e9040eccb57271d86fddc614230 (patch) | |
tree | 27386c5b4c2ab2ff3b7e8865f1300c7c54609c2b /src/cpu/o3/cpu.hh | |
parent | 679ca8b4cff6b683dff69a96eb8eb61716b61ad8 (diff) | |
download | gem5-cb5562bb15f32e9040eccb57271d86fddc614230.tar.xz |
methods to set taint
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r-- | src/cpu/o3/cpu.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 19b9a34e0..23e6f7434 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -399,6 +399,9 @@ class FullO3CPU : public BaseO3CPU void setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid); + /** taint a register */ + void setTaint(PhysRegIdPtr phys_reg); + uint64_t readIntReg(PhysRegIdPtr phys_reg); TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); |