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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit25884a87733cd35ef6613aaef9a8a08194267552 (patch)
tree3eb831102c76206ba5ba4e19b94810be67ce108f /src/cpu/o3/cpu.hh
parent32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (diff)
downloadgem5-25884a87733cd35ef6613aaef9a8a08194267552.tar.xz
Registers: Get rid of the float register width parameter.
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r--src/cpu/o3/cpu.hh16
1 files changed, 2 insertions, 14 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1289785dc..c077b2493 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -435,27 +435,17 @@ class FullO3CPU : public BaseO3CPU
TheISA::FloatReg readFloatReg(int reg_idx);
- TheISA::FloatReg readFloatReg(int reg_idx, int width);
-
TheISA::FloatRegBits readFloatRegBits(int reg_idx);
- TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
-
void setIntReg(int reg_idx, uint64_t val);
void setFloatReg(int reg_idx, TheISA::FloatReg val);
- void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
-
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
- void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
-
uint64_t readArchIntReg(int reg_idx, ThreadID tid);
- float readArchFloatRegSingle(int reg_idx, ThreadID tid);
-
- double readArchFloatRegDouble(int reg_idx, ThreadID tid);
+ float readArchFloatReg(int reg_idx, ThreadID tid);
uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
@@ -466,9 +456,7 @@ class FullO3CPU : public BaseO3CPU
*/
void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid);
-
- void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid);
+ void setArchFloatReg(int reg_idx, float val, ThreadID tid);
void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);