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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/cpu/o3/cpu.hh | |
parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r-- | src/cpu/o3/cpu.hh | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 7d7e4e24d..d97a2080d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -113,10 +113,8 @@ class FullO3CPU : public BaseO3CPU SwitchedOut }; -#if FULL_SYSTEM TheISA::ITB * itb; TheISA::DTB * dtb; -#endif /** Overall CPU status. */ Status _status; @@ -265,7 +263,6 @@ class FullO3CPU : public BaseO3CPU /** Registers statistics. */ void fullCPURegStats(); -#if FULL_SYSTEM /** Translates instruction requestion. */ Fault translateInstReq(RequestPtr &req, Thread *thread) { @@ -284,27 +281,6 @@ class FullO3CPU : public BaseO3CPU return this->dtb->translate(req, thread->getTC(), true); } -#else - /** Translates instruction requestion in syscall emulation mode. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data read request in syscall emulation mode. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data write request in syscall emulation mode. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - -#endif - /** Returns a specific port. */ Port *getPort(const std::string &if_name, int idx); |