Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)

Still need to add some code to fetch & commit stages

src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Add nextNPC

--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7

1 files changed, 7 insertions, 0 deletions

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index ff41a3306..8f4175c70 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #ifndef __CPU_O3_CPU_HH__
@@ -299,6 +300,12 @@ class FullO3CPU : public BaseFullCPU
     /** Sets the next PC of a specific thread. */
     void setNextPC(uint64_t val, unsigned tid);
 
+    /** Reads the next NPC of a specific thread. */
+    uint64_t readNextNPC(unsigned tid);
+
+    /** Sets the next NPC of a specific thread. */
+    void setNextNPC(uint64_t val, unsigned tid);
+
     /** Function to add instruction onto the head of the list of the
      *  instructions.  Used when new instructions are fetched.
      */