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| author | Gabe Black <gabeblack@google.com> | 2018-11-19 17:20:31 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-12-20 19:27:51 +0000 |
| commit | 88bbabe93f339f9db301caf43bf2cca2a0e8048c (patch) | |
| tree | 66323afaa9348f392deafe11d88973fd3034001b /src/cpu/o3/cpu.hh | |
| parent | 67d58e81825d7dff17def2cfeedf5d958141be55 (diff) | |
| download | gem5-88bbabe93f339f9db301caf43bf2cca2a0e8048c.tar.xz | |
arch, cpu: Remove float type accessors.
Use the binary accessors instead.
Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/o3/cpu.hh')
| -rw-r--r-- | src/cpu/o3/cpu.hh | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 19b9a34e0..4c4677615 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -401,8 +401,6 @@ class FullO3CPU : public BaseO3CPU uint64_t readIntReg(PhysRegIdPtr phys_reg); - TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); - TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; @@ -449,8 +447,6 @@ class FullO3CPU : public BaseO3CPU void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); - void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val); - void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); @@ -461,9 +457,7 @@ class FullO3CPU : public BaseO3CPU uint64_t readArchIntReg(int reg_idx, ThreadID tid); - float readArchFloatReg(int reg_idx, ThreadID tid); - - uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); + uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid); const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; /** Read architectural vector register for modification. */ @@ -502,9 +496,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setArchFloatReg(int reg_idx, float val, ThreadID tid); - - void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); + void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid); void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); |