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authorGabe Black <gblack@eecs.umich.edu>2007-04-13 13:59:31 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-13 13:59:31 +0000
commitc7f1cf1d58cf50118c18b1afc4c938eafba81492 (patch)
treebe5c82a40f629e12e88f6eb132c0fee27e352ae7 /src/cpu/o3/cpu.hh
parent6ec510385dd23f339f86f3ace4339c791affba89 (diff)
downloadgem5-c7f1cf1d58cf50118c18b1afc4c938eafba81492.tar.xz
Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
--HG-- extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r--src/cpu/o3/cpu.hh3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e71d05c8e..4b247e6e3 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -468,8 +468,7 @@ class FullO3CPU : public BaseO3CPU
/** Remove all instructions that are not currently in the ROB.
* There's also an option to not squash delay slot instructions.*/
- void removeInstsNotInROB(unsigned tid, bool squash_delay_slot,
- const InstSeqNum &delay_slot_seq_num);
+ void removeInstsNotInROB(unsigned tid);
/** Remove all instructions younger than the given sequence number. */
void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);