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authorAli Saidi <saidi@eecs.umich.edu>2006-06-17 17:17:43 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-06-17 17:17:43 -0400
commit8a1298822182c0ca01caddaa539bdb6a53927e57 (patch)
tree5677d2b7bf3a3d18295041167f1544def27f957c /src/cpu/o3/cpu.hh
parentb1fc43dd595e8f0420d9b61932c99f620df237a5 (diff)
parentd96d28e56d39eec0baa1377779119495cfbf4701 (diff)
downloadgem5-8a1298822182c0ca01caddaa539bdb6a53927e57.tar.xz
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c8670f1a39d6826870ca0934587f4cc71c94b0ab
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r--src/cpu/o3/cpu.hh13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index ff41a3306..b1ebcce9d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_CPU_HH__
@@ -56,13 +57,13 @@ class ThreadContext;
class MemObject;
class Process;
-class BaseFullCPU : public BaseCPU
+class BaseO3CPU : public BaseCPU
{
//Stuff that's pretty ISA independent will go here.
public:
typedef BaseCPU::Params Params;
- BaseFullCPU(Params *params);
+ BaseO3CPU(Params *params);
void regStats();
@@ -78,7 +79,7 @@ class BaseFullCPU : public BaseCPU
* tick() function for the CPU is defined here.
*/
template <class Impl>
-class FullO3CPU : public BaseFullCPU
+class FullO3CPU : public BaseO3CPU
{
public:
typedef TheISA::FloatReg FloatReg;
@@ -299,6 +300,12 @@ class FullO3CPU : public BaseFullCPU
/** Sets the next PC of a specific thread. */
void setNextPC(uint64_t val, unsigned tid);
+ /** Reads the next NPC of a specific thread. */
+ uint64_t readNextNPC(unsigned tid);
+
+ /** Sets the next NPC of a specific thread. */
+ void setNextNPC(uint64_t val, unsigned tid);
+
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
*/