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author | Gabe Black <gabeblack@google.com> | 2018-11-21 16:20:57 -0800 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-02-01 01:22:19 +0000 |
commit | a119a963240a35ab66a5baee3f77cfcd99c6bbbb (patch) | |
tree | c883d37ed479e92c23d881a48b8f2abec469faf7 /src/cpu/o3/cpu.hh | |
parent | fbdf0b689eb31543292f52c71d14152d8ff1156a (diff) | |
download | gem5-a119a963240a35ab66a5baee3f77cfcd99c6bbbb.tar.xz |
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r-- | src/cpu/o3/cpu.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 9612b3667..aabac5fea 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -463,7 +463,7 @@ class FullO3CPU : public BaseO3CPU VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); - TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); + RegVal readCCReg(PhysRegIdPtr phys_reg); void setIntReg(PhysRegIdPtr phys_reg, RegVal val); @@ -475,7 +475,7 @@ class FullO3CPU : public BaseO3CPU void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); - void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); + void setCCReg(PhysRegIdPtr phys_reg, RegVal val); RegVal readArchIntReg(int reg_idx, ThreadID tid); @@ -514,7 +514,7 @@ class FullO3CPU : public BaseO3CPU VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); - TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); + RegVal readArchCCReg(int reg_idx, ThreadID tid); /** Architectural register accessors. Looks up in the commit * rename table to obtain the true physical index of the @@ -533,7 +533,7 @@ class FullO3CPU : public BaseO3CPU void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid); - void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); + void setArchCCReg(int reg_idx, RegVal val, ThreadID tid); /** Sets the commit PC state of a specific thread. */ void pcState(const TheISA::PCState &newPCState, ThreadID tid); |