diff options
author | Gabe Black <gabeblack@google.com> | 2019-08-17 01:15:39 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-08-28 02:14:29 +0000 |
commit | b4e3e2f4a4dfa3a05d068ab33eb50a749326f2c5 (patch) | |
tree | 352cb6a0d1e920cbe649f82893192e7fd96b6a3a /src/cpu/o3/cpu.hh | |
parent | c387a212d98024e42e4267ff364c2976f976d666 (diff) | |
download | gem5-b4e3e2f4a4dfa3a05d068ab33eb50a749326f2c5.tar.xz |
cpu: Move O3's data port into the LSQ.
That's where it's used, and putting it there avoids having to pass
around the port using the top level getDataPort function.
Change-Id: I0dea25d0c5f4bb3f58a6574a8f2b2d242784caf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/o3/cpu.hh')
-rw-r--r-- | src/cpu/o3/cpu.hh | 52 |
1 files changed, 5 insertions, 47 deletions
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 68ad95b18..778c55bac 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -158,49 +158,6 @@ class FullO3CPU : public BaseO3CPU virtual void recvReqRetry(); }; - /** - * DcachePort class for the load/store queue. - */ - class DcachePort : public MasterPort - { - protected: - - /** Pointer to LSQ. */ - LSQ<Impl> *lsq; - FullO3CPU<Impl> *cpu; - - public: - /** Default constructor. */ - DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) - : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), - cpu(_cpu) - { } - - protected: - - /** Timing version of receive. Handles writing back and - * completing the load or store that has returned from - * memory. */ - virtual bool recvTimingResp(PacketPtr pkt); - virtual void recvTimingSnoopReq(PacketPtr pkt); - - virtual void recvFunctionalSnoop(PacketPtr pkt) - { - // @todo: Is there a need for potential invalidation here? - } - - /** Handles doing a retry of the previous send. */ - virtual void recvReqRetry(); - - /** - * As this CPU requires snooping to maintain the load store queue - * change the behaviour from the base CPU port. - * - * @return true since we have to snoop - */ - virtual bool isSnooping() const { return true; } - }; - /** The tick event used for scheduling CPU ticks. */ EventFunctionWrapper tickEvent; @@ -675,9 +632,6 @@ class FullO3CPU : public BaseO3CPU /** Instruction port. Note that it has to appear after the fetch stage. */ IcachePort icachePort; - /** Data port. Note that it has to appear after the iew stages */ - DcachePort dcachePort; - public: /** Enum to give each stage a specific index, so when calling * activateStage() or deactivateStage(), they can specify which stage @@ -812,7 +766,11 @@ class FullO3CPU : public BaseO3CPU MasterPort &getInstPort() override { return icachePort; } /** Get the dcache port (used to find block size for translations). */ - MasterPort &getDataPort() override { return dcachePort; } + MasterPort & + getDataPort() override + { + return this->iew.ldstQueue.getDataPort(); + } /** Stat for total number of times the CPU is descheduled. */ Stats::Scalar timesIdled; |