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authorKorey Sewell <ksewell@umich.edu>2006-07-23 13:41:53 -0400
committerKorey Sewell <ksewell@umich.edu>2006-07-23 13:41:53 -0400
commit6e969c31c7c0671ce201f40dd67afad2e9fee832 (patch)
tree1a7a5bc1e52dd54ff3319837fa87c018d8dd08b0 /src/cpu/o3/decode.hh
parentf9729e999f71895f6b53f8189bdff535e7c7b70e (diff)
parent19ca97af79f3a40111991b4f8375592c7ede65fa (diff)
downloadgem5-6e969c31c7c0671ce201f40dd67afad2e9fee832.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
Diffstat (limited to 'src/cpu/o3/decode.hh')
-rw-r--r--src/cpu/o3/decode.hh13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 7f5ecbc26..4a845e670 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -276,6 +276,19 @@ class DefaultDecode
/** Maximum size of the skid buffer. */
unsigned skidBufferMax;
+ /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
+ Addr bdelayDoneSeqNum[Impl::MaxThreads];
+
+ /** Instruction used for squashing branch (used for MIPS)*/
+ DynInstPtr squashInst[Impl::MaxThreads];
+
+ /** Tells when their is a pending delay slot inst. to send
+ * to rename. If there is, then wait squash after the next
+ * instruction (used for MIPS).
+ */
+ bool squashAfterDelaySlot[Impl::MaxThreads];
+
+
/** Stat for total number of idle cycles. */
Stats::Scalar<> decodeIdleCycles;
/** Stat for total number of blocked cycles. */