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author | Kevin Lim <ktlim@umich.edu> | 2006-06-05 18:14:39 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-06-05 18:14:39 -0400 |
commit | 090496bf2d4c0f55f7f5869a374b4ec3826bccbc (patch) | |
tree | 4be899992389661b5cd60f2f067e39e719577430 /src/cpu/o3/decode_impl.hh | |
parent | 295c7a908cfeecc7276f559ff53282a177f4eb66 (diff) | |
download | gem5-090496bf2d4c0f55f7f5869a374b4ec3826bccbc.tar.xz |
Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.
src/cpu/base_dyn_inst.cc:
Delete the allocated data in destructor.
src/cpu/base_dyn_inst.hh:
Only copy the addresses if the translation succeeded.
src/cpu/o3/alpha_cpu.hh:
Return actual translating port.
Don't panic on setNextNPC() as it's always called, regardless of the architecture, when the process initializes.
src/cpu/o3/alpha_cpu_impl.hh:
Pass in memobject to the thread state in SE mode.
src/cpu/o3/commit_impl.hh:
Initialize all variables.
src/cpu/o3/decode_impl.hh:
Handle early resolution of branches properly.
src/cpu/o3/fetch.hh:
Switch structure back to requests.
src/cpu/o3/fetch_impl.hh:
Initialize all variables, create/delete requests properly.
src/cpu/o3/lsq_unit.hh:
Include sender state along with the packet. Also include a more generic writeback event that's only used for stores forwarding data to loads.
src/cpu/o3/lsq_unit_impl.hh:
Redo writeback code to support the response path of the memory system.
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit_impl.hh:
Wrap variables in #ifdefs.
src/cpu/o3/store_set.cc:
Include to get panic() function.
src/cpu/o3/thread_state.hh:
Create with MemObject as well.
src/cpu/thread_state.hh:
Have a translating port in the thread state object.
src/python/m5/objects/AlphaFullCPU.py:
Mem parameter no longer needed.
--HG--
extra : convert_revision : a99381fb25cb183322882ce20935a6f3d1f2b64d
Diffstat (limited to 'src/cpu/o3/decode_impl.hh')
-rw-r--r-- | src/cpu/o3/decode_impl.hh | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 64b04bc3d..8a6ea6626 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -280,7 +280,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; toFetch->decodeInfo[tid].predIncorrect = true; toFetch->decodeInfo[tid].squash = true; - toFetch->decodeInfo[tid].nextPC = inst->readNextPC(); + toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); toFetch->decodeInfo[tid].branchTaken = inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); @@ -723,9 +723,8 @@ DefaultDecode<Impl>::decodeInsts(unsigned tid) // Go ahead and compute any PC-relative branches. if (inst->isDirectCtrl() && inst->isUncondCtrl()) { ++decodeBranchResolved; - inst->setNextPC(inst->branchTarget()); - if (inst->mispredicted()) { + if (inst->branchTarget() != inst->readPredTarg()) { ++decodeBranchMispred; // Might want to set some sort of boolean and just do |