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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:04 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:04 -0600
commit4a1814bd524e7444f57dcd1ea24070fd7b375af3 (patch)
treeffab2e2662c660ecd8905efbbf98efafb1ddd2ec /src/cpu/o3/dyn_inst.cc
parentd4767f440a7a8bfefa0851726b729b8d30a654a5 (diff)
downloadgem5-4a1814bd524e7444f57dcd1ea24070fd7b375af3.tar.xz
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation.
Diffstat (limited to 'src/cpu/o3/dyn_inst.cc')
0 files changed, 0 insertions, 0 deletions