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authorIru Cai <mytbk920423@gmail.com>2019-04-15 23:21:46 +0800
committerIru Cai <mytbk920423@gmail.com>2019-04-15 23:21:46 +0800
commit24b8aa03c307e799a8766952aeabac763f98010a (patch)
treede8c6be5d4afb5fe9662bfe2a8f716e91f0788c0 /src/cpu/o3/dyn_inst.hh
parent08d003162e7a0bda11a5e4e96e0a6fa203f2c1f3 (diff)
downloadgem5-24b8aa03c307e799a8766952aeabac763f98010a.tar.xz
Add IFT debug flags
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
-rw-r--r--src/cpu/o3/dyn_inst.hh12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index d3c67c4cb..22b4bb12a 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -53,6 +53,7 @@
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
#include "cpu/reg_class.hh"
+#include "debug/IFT.hh"
class Packet;
@@ -416,8 +417,12 @@ class BaseO3DynInst : public BaseDynInst<Impl>
BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
}
- void taintDestRegs(bool istaint)
+ void taintDestRegs(bool istaint, const char *reason)
{
+ DPRINTF(IFT, "%s dst registers of instruction PC: %s [sn:%i] because %s\n",
+ istaint?"Tainting":"Untainting",
+ this->pcState(), this->seqNum,
+ reason);
isTainted = istaint;
for (size_t i = 0; i < this->numDestRegs(); i++) {
auto dstreg = _destRegIdx[i];
@@ -431,11 +436,16 @@ class BaseO3DynInst : public BaseDynInst<Impl>
bool srcTainted(void)
{
+ DPRINTF(IFT, "checking instruction PC: %s [sn:%i] for tainted registers.\n",
+ this->pcState(), this->seqNum);
bool result = false;
for (size_t i = 0; i < this->numSrcRegs(); i++) {
auto src = _srcRegIdx[i];
result |= cpu->regTainted(src);
}
+ DPRINTF(IFT, "source registers of instruction PC: %s [sn:%i] is %s\n",
+ this->pcState(), this->seqNum,
+ result?"tainted":"not tainted");
return result;
}