cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 18 insertions, 1 deletions

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 6740c601d..d19e4d461 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -74,6 +74,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::CCReg   CCReg;
+    typedef TheISA::VectorReg VectorReg;
 
     /** Misc register index type. */
     typedef TheISA::MiscReg  MiscReg;
@@ -206,7 +207,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     void forwardOldRegs()
     {
-
         for (int idx = 0; idx < this->numDestRegs(); idx++) {
             PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
             TheISA::RegIndex original_dest_reg =
@@ -224,6 +224,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
                 this->setCCRegOperand(this->staticInst.get(), idx,
                                       this->cpu->readCCReg(prev_phys_reg));
                 break;
+              case VectorRegClass:
+                this->setVectorRegOperand(this->staticInst.get(), idx,
+                        this->cpu->readVectorReg(prev_phys_reg));
+                break;
+
               case MiscRegClass:
                 // no need to forward misc reg values
                 break;
@@ -272,6 +277,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         return this->cpu->readCCReg(this->_srcRegIdx[idx]);
     }
 
+    const VectorReg &readVectorRegOperand(const StaticInst *si, int idx)
+    {
+        return this->cpu->readVectorReg(this->_srcRegIdx[idx]);
+    }
+
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
@@ -300,6 +310,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
     }
 
+    void setVectorRegOperand(const StaticInst *si, int idx,
+                             const VectorReg &val)
+    {
+        this->cpu->setVectorReg(this->_destRegIdx[idx], val);
+        BaseDynInst<Impl>::setVectorRegOperand(si, idx, val);
+    }
+
 #if THE_ISA == MIPS_ISA
     MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
     {