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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
| commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
| tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/o3/dyn_inst.hh | |
| parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
| download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz | |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index d19e4d461..6740c601d 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -74,7 +74,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; - typedef TheISA::VectorReg VectorReg; /** Misc register index type. */ typedef TheISA::MiscReg MiscReg; @@ -207,6 +206,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> void forwardOldRegs() { + for (int idx = 0; idx < this->numDestRegs(); idx++) { PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); TheISA::RegIndex original_dest_reg = @@ -224,11 +224,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> this->setCCRegOperand(this->staticInst.get(), idx, this->cpu->readCCReg(prev_phys_reg)); break; - case VectorRegClass: - this->setVectorRegOperand(this->staticInst.get(), idx, - this->cpu->readVectorReg(prev_phys_reg)); - break; - case MiscRegClass: // no need to forward misc reg values break; @@ -277,11 +272,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> return this->cpu->readCCReg(this->_srcRegIdx[idx]); } - const VectorReg &readVectorRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readVectorReg(this->_srcRegIdx[idx]); - } - /** @todo: Make results into arrays so they can handle multiple dest * registers. */ @@ -310,13 +300,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> BaseDynInst<Impl>::setCCRegOperand(si, idx, val); } - void setVectorRegOperand(const StaticInst *si, int idx, - const VectorReg &val) - { - this->cpu->setVectorReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setVectorRegOperand(si, idx, val); - } - #if THE_ISA == MIPS_ISA MiscReg readRegOtherThread(int misc_reg, ThreadID tid) { |