diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:02 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:02 -0600 |
commit | 0f9a3671b6d12f887501bc80ca50bb23c383686d (patch) | |
tree | 5406b672b12e85c0654362272350cb50057be595 /src/cpu/o3/dyn_inst.hh | |
parent | 96375409ea7a5593ddd7f4f723db349921f35142 (diff) | |
download | gem5-0f9a3671b6d12f887501bc80ca50bb23c383686d.tar.xz |
ARM: Add support for moving predicated false dest operands from sources.
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
-rw-r--r-- | src/cpu/o3/dyn_inst.hh | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index b62068111..487c284e6 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -181,6 +181,18 @@ class BaseO3DynInst : public BaseDynInst<Impl> this->thread->inSyscall = in_syscall; } + void forwardOldRegs() + { + + for (int idx = 0; idx < this->numDestRegs(); idx++) { + PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); + TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx); + if (original_dest_reg < TheISA::FP_Base_DepTag) + this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg)); + else if (original_dest_reg < TheISA::Ctrl_Base_DepTag) + this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); + } + } #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); |