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authorNathanael Premillieu <nathanael.premillieu@arm.com>2017-04-05 12:46:06 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch)
tree7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/o3/dyn_inst.hh
parent864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff)
downloadgem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
-rw-r--r--src/cpu/o3/dyn_inst.hh25
1 files changed, 12 insertions, 13 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8ab9979d2..3096e5946 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -67,15 +67,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
typedef TheISA::MachInst MachInst;
/** Extended machine instruction type. */
typedef TheISA::ExtMachInst ExtMachInst;
- /** Logical register index type. */
- typedef TheISA::RegIndex RegIndex;
- /** Integer register index type. */
+ /** Register types. */
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
- /** Misc register index type. */
+ /** Misc register type. */
typedef TheISA::MiscReg MiscReg;
enum {
@@ -172,9 +170,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
*/
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
- return this->cpu->readMiscReg(
- si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
- this->threadNumber);
+ RegId reg = si->srcRegIdx(idx);
+ assert(reg.regClass == MiscRegClass);
+ return this->cpu->readMiscReg(reg.regIdx, this->threadNumber);
}
/** Sets a misc. register, including any side-effects the write
@@ -183,8 +181,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
- int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
- setMiscReg(misc_reg, val);
+ RegId reg = si->destRegIdx(idx);
+ assert(reg.regClass == MiscRegClass);
+ setMiscReg(reg.regIdx, val);
}
/** Called at the commit stage to update the misc. registers. */
@@ -209,9 +208,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
for (int idx = 0; idx < this->numDestRegs(); idx++) {
PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
- TheISA::RegIndex original_dest_reg =
+ RegId original_dest_reg =
this->staticInst->destRegIdx(idx);
- switch (regIdxToClass(original_dest_reg)) {
+ switch (original_dest_reg.regClass) {
case IntRegClass:
this->setIntRegOperand(this->staticInst.get(), idx,
this->cpu->readIntReg(prev_phys_reg));
@@ -301,13 +300,13 @@ class BaseO3DynInst : public BaseDynInst<Impl>
}
#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
+ MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid)
{
panic("MIPS MT not defined for O3 CPU.\n");
return 0;
}
- void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
+ void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid)
{
panic("MIPS MT not defined for O3 CPU.\n");
}