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| author | Stephen Hines <hines@cs.fsu.edu> | 2008-02-05 23:44:13 -0500 |
|---|---|---|
| committer | Stephen Hines <hines@cs.fsu.edu> | 2008-02-05 23:44:13 -0500 |
| commit | 0ccf9a2c3751f160d7d51153ef468a60b4daf8d0 (patch) | |
| tree | 3f5d77b729818492d27996adbc69b472f6fd4da7 /src/cpu/o3/dyn_inst.hh | |
| parent | ca313e23033cd3f2ef827edf9a442ed1ae3d087f (diff) | |
| download | gem5-0ccf9a2c3751f160d7d51153ef468a60b4daf8d0.tar.xz | |
Add base ARM code to M5
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index c37f8007e..a1f9e0591 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -49,6 +49,10 @@ template <class Impl> class X86DynInst; struct X86SimpleImpl; typedef X86DynInst<X86SimpleImpl> O3DynInst; +#elif THE_ISA == ARM_ISA + template <class Impl> class ArmDynInst; + struct ArmSimpleImpl; + typedef ArmDynInst<ArmSimpleImpl> O3DynInst; #else #error "O3DynInst not defined for this ISA" #endif |