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authorYasuko Eckert <yasuko.eckert@amd.com>2013-10-15 14:22:44 -0400
committerYasuko Eckert <yasuko.eckert@amd.com>2013-10-15 14:22:44 -0400
commit2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch)
tree040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/dyn_inst.hh
parent552622184752dc798bc81f9b0b395db68aee9511 (diff)
downloadgem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz
cpu: add a condition-code register class
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/dyn_inst.hh')
-rw-r--r--src/cpu/o3/dyn_inst.hh18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 15a82851b..5477f46d6 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -78,6 +78,9 @@ class BaseO3DynInst : public BaseDynInst<Impl>
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
+#ifdef ISA_HAS_CC_REGS
+ typedef TheISA::CCReg CCReg;
+#endif
/** Misc register index type. */
typedef TheISA::MiscReg MiscReg;
@@ -222,6 +225,10 @@ class BaseO3DynInst : public BaseDynInst<Impl>
this->setFloatRegOperandBits(this->staticInst.get(), idx,
this->cpu->readFloatRegBits(prev_phys_reg));
break;
+ case CCRegClass:
+ this->setCCRegOperand(this->staticInst.get(), idx,
+ this->cpu->readCCReg(prev_phys_reg));
+ break;
case MiscRegClass:
// no need to forward misc reg values
break;
@@ -265,6 +272,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
+ uint64_t readCCRegOperand(const StaticInst *si, int idx)
+ {
+ return this->cpu->readCCReg(this->_srcRegIdx[idx]);
+ }
+
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
@@ -287,6 +299,12 @@ class BaseO3DynInst : public BaseDynInst<Impl>
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
+ void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
+ {
+ this->cpu->setCCReg(this->_destRegIdx[idx], val);
+ BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
+ }
+
#if THE_ISA == MIPS_ISA
uint64_t readRegOtherThread(int misc_reg)
{