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author | Ali Saidi <saidi@eecs.umich.edu> | 2008-10-20 16:22:59 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2008-10-20 16:22:59 -0400 |
commit | b760b99f4d9f5469d88c67ae8a06e5f9543a43e7 (patch) | |
tree | 39cb41ec58be172c0f4b65162ae637be42bbabb0 /src/cpu/o3/dyn_inst_impl.hh | |
parent | 4fac54f227f0ee0ee169955cb2510609434f7d85 (diff) | |
download | gem5-b760b99f4d9f5469d88c67ae8a06e5f9543a43e7.tar.xz |
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.
Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.
Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
Diffstat (limited to 'src/cpu/o3/dyn_inst_impl.hh')
-rw-r--r-- | src/cpu/o3/dyn_inst_impl.hh | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh index 3b713ea8f..6398a3afe 100644 --- a/src/cpu/o3/dyn_inst_impl.hh +++ b/src/cpu/o3/dyn_inst_impl.hh @@ -125,11 +125,43 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) #if FULL_SYSTEM template <class Impl> +Fault +BaseO3DynInst<Impl>::hwrei() +{ +#if THE_ISA == ALPHA_ISA + // Can only do a hwrei when in pal mode. + if (!(this->readPC() & 0x3)) + return new AlphaISA::UnimplementedOpcodeFault; + + // Set the next PC based on the value of the EXC_ADDR IPR. + this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, + this->threadNumber)); + + // Tell CPU to clear any state it needs to if a hwrei is taken. + this->cpu->hwrei(this->threadNumber); +#else + +#endif + // FIXME: XXX check for interrupts? XXX + return NoFault; +} + +template <class Impl> void BaseO3DynInst<Impl>::trap(Fault fault) { this->cpu->trap(fault, this->threadNumber); } + +template <class Impl> +bool +BaseO3DynInst<Impl>::simPalCheck(int palFunc) +{ +#if THE_ISA != ALPHA_ISA + panic("simPalCheck called, but PAL only exists in Alpha!\n"); +#endif + return this->cpu->simPalCheck(palFunc, this->threadNumber); +} #else template <class Impl> void |