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| author | Kevin Lim <ktlim@umich.edu> | 2006-07-13 13:09:29 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-07-13 13:09:29 -0400 |
| commit | 2af213022ce6d58eee2809f300d7450e89a4bce9 (patch) | |
| tree | 304393e05611feffdcd18707384942b55e6a7764 /src/cpu/o3/fetch.hh | |
| parent | a0a952d5ff8e27d34c7fa68fe5199c57670c53d1 (diff) | |
| download | gem5-2af213022ce6d58eee2809f300d7450e89a4bce9.tar.xz | |
Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
--HG--
extra : convert_revision : 07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
Diffstat (limited to 'src/cpu/o3/fetch.hh')
| -rw-r--r-- | src/cpu/o3/fetch.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 0331cf07f..931919af8 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -407,6 +407,9 @@ class DefaultFetch /** The PC of the cacheline that has been loaded. */ Addr cacheDataPC[Impl::MaxThreads]; + /** Whether or not the cache data is valid. */ + bool cacheDataValid[Impl::MaxThreads]; + /** Size of instructions. */ int instSize; |