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authorKevin Lim <ktlim@umich.edu>2006-07-07 17:33:24 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-07 17:33:24 -0400
commit8ade33d324218737c815935120307153975eeadc (patch)
tree587a5dce799c0f5a2901dd1eaf452b2ae1ccfbc5 /src/cpu/o3/fetch.hh
parent744e0055b704f4c202e765f46e4fd4f56e1b847c (diff)
downloadgem5-8ade33d324218737c815935120307153975eeadc.tar.xz
Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
Diffstat (limited to 'src/cpu/o3/fetch.hh')
-rw-r--r--src/cpu/o3/fetch.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index a793c7361..85654cebc 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -162,6 +162,9 @@ class DefaultFetch
/** Registers statistics. */
void regStats();
+ /** Returns the icache port. */
+ Port *getIcachePort() { return icachePort; }
+
/** Sets CPU pointer. */
void setCPU(O3CPU *cpu_ptr);