diff options
| author | Gabe Black <gabeblack@google.com> | 2019-08-17 01:32:23 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-08-28 02:14:53 +0000 |
| commit | b16e525e4073b27f70bf6cf960313ea76cf6ed54 (patch) | |
| tree | a48adae9a66d1f563cdc100d2697a49709474f1a /src/cpu/o3/fetch.hh | |
| parent | b4e3e2f4a4dfa3a05d068ab33eb50a749326f2c5 (diff) | |
| download | gem5-b16e525e4073b27f70bf6cf960313ea76cf6ed54.tar.xz | |
cpu: Move the instruction port into o3's fetch stage.
That's where it's used, and that avoids having to pass it around using
the top level getInstPort accessor.
Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/o3/fetch.hh')
| -rw-r--r-- | src/cpu/o3/fetch.hh | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 3cf0773fd..b8766ad77 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -59,6 +59,8 @@ #include "sim/probe/probe.hh" struct DerivO3CPUParams; +template <class Impl> +class FullO3CPU; /** * DefaultFetch class handles both single threaded and SMT fetch. Its @@ -85,6 +87,31 @@ class DefaultFetch /** Typedefs from ISA. */ typedef TheISA::MachInst MachInst; + /** + * IcachePort class for instruction fetch. + */ + class IcachePort : public MasterPort + { + protected: + /** Pointer to fetch. */ + DefaultFetch<Impl> *fetch; + + public: + /** Default constructor. */ + IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) + : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) + { } + + protected: + + /** Timing version of receive. Handles setting fetch to the + * proper status to start fetching. */ + virtual bool recvTimingResp(PacketPtr pkt); + + /** Handles doing a retry of a failed fetch. */ + virtual void recvReqRetry(); + }; + class FetchTranslation : public BaseTLB::Translation { protected: @@ -353,6 +380,8 @@ class DefaultFetch /** The decoder. */ TheISA::Decoder *decoder[Impl::MaxThreads]; + MasterPort &getInstPort() { return icachePort; } + private: DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, @@ -511,6 +540,9 @@ class DefaultFetch */ bool interruptPending; + /** Instruction port. Note that it has to appear after the fetch stage. */ + IcachePort icachePort; + /** Set to true if a pipelined I-cache request should be issued. */ bool issuePipelinedIfetch[Impl::MaxThreads]; |