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author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 11:35:40 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-16 11:35:40 -0500 |
commit | 9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5 (patch) | |
tree | 50e7a435de1e0f5638eba9b1b030e79daaf1aee0 /src/cpu/o3/fetch.hh | |
parent | 4da37bcd1bc2c42ce5f297a58b4b4bffa4e8cd4f (diff) | |
parent | f4f00c5ae98c069f79a8b56ed93284daf7532c7e (diff) | |
download | gem5-9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5.tar.xz |
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
Hand Merge
--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
Diffstat (limited to 'src/cpu/o3/fetch.hh')
-rw-r--r-- | src/cpu/o3/fetch.hh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index e880e14e4..0371cd2bc 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -239,13 +239,13 @@ class DefaultFetch bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid); /** Squashes a specific thread and resets the PC. */ - inline void doSquash(const Addr &new_PC, unsigned tid); + inline void doSquash(const Addr &new_PC, const Addr &new_NPC, unsigned tid); /** Squashes a specific thread and resets the PC. Also tells the CPU to * remove any instructions between fetch and decode that should be sqaushed. */ - void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num, - unsigned tid); + void squashFromDecode(const Addr &new_PC, const Addr &new_NPC, + const InstSeqNum &seq_num, unsigned tid); /** Checks if a thread is stalled. */ bool checkStall(unsigned tid) const; @@ -259,7 +259,8 @@ class DefaultFetch * remove any instructions that are not in the ROB. The source of this * squash should be the commit stage. */ - void squash(const Addr &new_PC, const InstSeqNum &seq_num, + void squash(const Addr &new_PC, const Addr &new_NPC, + const InstSeqNum &seq_num, bool squash_delay_slot, unsigned tid); /** Ticks the fetch stage, processing all inputs signals and fetching |