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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-06-17 17:17:43 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-06-17 17:17:43 -0400 |
| commit | 8a1298822182c0ca01caddaa539bdb6a53927e57 (patch) | |
| tree | 5677d2b7bf3a3d18295041167f1544def27f957c /src/cpu/o3/fetch.hh | |
| parent | b1fc43dd595e8f0420d9b61932c99f620df237a5 (diff) | |
| parent | d96d28e56d39eec0baa1377779119495cfbf4701 (diff) | |
| download | gem5-8a1298822182c0ca01caddaa539bdb6a53927e57.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : c8670f1a39d6826870ca0934587f4cc71c94b0ab
Diffstat (limited to 'src/cpu/o3/fetch.hh')
| -rw-r--r-- | src/cpu/o3/fetch.hh | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 962d46437..790c28f09 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Kevin Lim + * Korey Sewell */ #ifndef __CPU_O3_FETCH_HH__ @@ -57,7 +58,7 @@ class DefaultFetch typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::Params Params; /** Typedefs from the CPU policy. */ @@ -164,7 +165,7 @@ class DefaultFetch void regStats(); /** Sets CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); @@ -296,8 +297,8 @@ class DefaultFetch int branchCount(); private: - /** Pointer to the FullCPU. */ - FullCPU *cpu; + /** Pointer to the O3CPU. */ + O3CPU *cpu; /** Time buffer interface. */ TimeBuffer<TimeStruct> *timeBuffer; @@ -335,6 +336,15 @@ class DefaultFetch /** Per-thread next PC. */ Addr nextPC[Impl::MaxThreads]; +#if THE_ISA != ALPHA_ISA + /** Per-thread next Next PC. + * This is not a real register but is used for + * architectures that use a branch-delay slot. + * (such as MIPS or Sparc) + */ + Addr nextNPC[Impl::MaxThreads]; +#endif + /** Memory request used to access cache. */ RequestPtr memReq[Impl::MaxThreads]; |