O3: Fix issue with interrupts/faults occuring in the middle of a macro-op

This patch fixes two problems with the O3 cpu model. The first is an issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to issue
if the next line faults a fault is attached to a micro-op in the currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.

A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is incorrect
in the case of a macro-op as the current location might not be interruptable.

1 files changed, 3 insertions, 0 deletions

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 53f0f631e..92affc6db 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -403,6 +403,9 @@ class DefaultFetch
 
     StaticInstPtr macroop[Impl::MaxThreads];
 
+    /** Can the fetch stage redirect from an interrupt on this instruction? */
+    bool delayedCommit[Impl::MaxThreads];
+
     /** Memory request used to access cache. */
     RequestPtr memReq[Impl::MaxThreads];