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author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2011-01-18 16:30:01 -0600 |
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committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2011-01-18 16:30:01 -0600 |
commit | 96375409ea7a5593ddd7f4f723db349921f35142 (patch) | |
tree | 38668fb81cc4d07cb037221dcb2d576d327c1309 /src/cpu/o3/fetch.hh | |
parent | 965a01d913f71570150c839ffc7376084d0fed88 (diff) | |
download | gem5-96375409ea7a5593ddd7f4f723db349921f35142.tar.xz |
O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
When this condition occurs the cpu should restart the fetch stage to fetch from
the original execution path. Fault handling in the commit stage is cleaned up a
little bit so the control flow is simplier. Finally, if an instruction is being
used to carry a fault it isn't executed, so the fault propagates appropriately.
Diffstat (limited to 'src/cpu/o3/fetch.hh')
-rw-r--r-- | src/cpu/o3/fetch.hh | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 87dde1da8..b86ccf81e 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -244,6 +244,15 @@ class DefaultFetch */ bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc); + + /** Check if an interrupt is pending and that we need to handle + */ + bool + checkInterrupt(Addr pc) + { + return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); + } + /** Squashes a specific thread and resets the PC. */ inline void doSquash(const TheISA::PCState &newPC, ThreadID tid); |