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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-07 18:50:33 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-07 18:50:33 -0500 |
commit | ed22eb781dc7714c1b2ca17cf17824917e38319c (patch) | |
tree | 776fa030f78b810b4964334ddb81802adff6b6d1 /src/cpu/o3/fetch.hh | |
parent | 03be92f23b36ba69bfee179f97cd5af23c0f6e2c (diff) | |
download | gem5-ed22eb781dc7714c1b2ca17cf17824917e38319c.tar.xz |
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Diffstat (limited to 'src/cpu/o3/fetch.hh')
0 files changed, 0 insertions, 0 deletions