Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)

Still need to add some code to fetch & commit stages

src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Add nextNPC

--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7

1 files changed, 10 insertions, 0 deletions

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 962d46437..c2d91a379 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *          Korey Sewell
  */
 
 #ifndef __CPU_O3_FETCH_HH__
@@ -335,6 +336,15 @@ class DefaultFetch
     /** Per-thread next PC. */
     Addr nextPC[Impl::MaxThreads];
 
+#if THE_ISA != ALPHA_ISA
+    /** Per-thread next Next PC.
+     *  This is not a real register but is used for
+     *  architectures that use a branch-delay slot.
+     *  (such as MIPS or Sparc)
+     */
+    Addr nextNPC[Impl::MaxThreads];
+#endif
+
     /** Memory request used to access cache. */
     RequestPtr memReq[Impl::MaxThreads];