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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
| commit | 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch) | |
| tree | 4c212f665de2628eac6f84d389de7a79b6d0b933 /src/cpu/o3/fetch_impl.hh | |
| parent | 08043c777f1f05f5e14581950013461f328965be (diff) | |
| download | gem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz | |
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 79a4f2b7a..f9cc78c18 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -601,7 +601,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid memReq[tid] = mem_req; // Translate the instruction request. - fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC()); + fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(), + false, true); // In the case of faults, the fetch stage may need to stall and wait // for the ITB miss to be handled. |