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authorMin Kyu Jeong <minkyu.jeong@arm.com>2011-01-18 16:30:01 -0600
committerMin Kyu Jeong <minkyu.jeong@arm.com>2011-01-18 16:30:01 -0600
commit96375409ea7a5593ddd7f4f723db349921f35142 (patch)
tree38668fb81cc4d07cb037221dcb2d576d327c1309 /src/cpu/o3/fetch_impl.hh
parent965a01d913f71570150c839ffc7376084d0fed88 (diff)
downloadgem5-96375409ea7a5593ddd7f4f723db349921f35142.tar.xz
O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propagates appropriately.
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r--src/cpu/o3/fetch_impl.hh18
1 files changed, 15 insertions, 3 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 28ef423c4..1875d9c50 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -550,7 +562,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid,
DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
tid);
return false;
- } else if (interruptPending && !(pc & 0x3)) {
+ } else if (checkInterrupt(pc)) {
// Hold off fetch from getting new instructions when:
// Cache is blocked, or
// while an interrupt is pending and we're not in PAL mode, or
@@ -1250,8 +1262,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
fetchStatus[tid] = TrapPending;
status_change = true;
- DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s",
- tid, fault->name(), thisPC);
+ DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s, sending nop "
+ "[sn:%lli]\n", tid, fault->name(), thisPC, inst_seq);
}
}